1. Field of the Invention
The present invention relates to a solid-state imaging device, and more particularly, to a MOS solid-state imaging device and load current source circuit.
2. Description of the Related Art
MOS (Metal Oxide Semiconductor) solid-state imaging devices are known as solid-state imaging devices. In a MOS solid-state imaging device, the potential resulting from the charge generated by a photoelectric conversion element is amplified by an amplifying transistor, after which the amplified signal is read out. For example, a MOS solid-state imaging device has been proposed that reads out the reset levels of the reference and pixel signals output to the vertical signal lines by the amplifying transistors in the pixel circuits and outputs the difference between the two levels (refer, for example, to Japanese Patent Laid-Open No. 2002-217397 (FIG. 1)). Reading out the reference and pixel signals as described above is called correlated double sampling. Here, a brief description will be given below of a configuration example of a MOS solid-state imaging device operable to handle correlated double sampling with reference to the accompanying drawing.
FIG. 8 is a circuit diagram illustrating a configuration example of a solid-state imaging device in related art. This solid-state imaging device 800 in related art includes a timing control circuit 810, row scan circuit 820, column scan circuit 830, pixel array section 840 and load current source circuit 860. The solid-state imaging device 800 further includes a signal readout circuit 880 and signal processing section 890.
The pixel array section 840 includes a plurality of pixel circuits 850 arranged in a two-dimensional matrix (n by m). The pixel array section 840 further includes horizontal line (HL) sets 829 that are arranged one set in each row of the pixel circuits 850 and vertical signal lines (VSL) 839 that are arranged one in each column of the pixel circuits 850.
On the other hand, the load current source circuit 860 includes a reference transistor 861 and load current supply circuits 870 that are arranged one in each column of the pixel circuits 850. Further, each of the load current supply circuits 870 includes a load transistor 874 and parasitic capacitor 879. Still further, the signal readout circuit 880 includes a plurality of CDS (Correlated Double Sampling) circuits 881 and 882 that are arranged one in each column of the pixel circuits 850.
The timing control circuit 810 controls the timings of the image signal generation performed by the row scan circuit 820, column scan circuit 830 and pixel array section 840. The timing control circuit 810 generates a timing control signal used to generate an image signal. The image signal is generated as the signals, output from the pixel circuits 850 of the pixel array section 840 on a row-by-row basis, are read out in the column direction. That is, the timing control circuit 810 controls the timings for the generation of an image signal using column parallel readout.
The timing control circuit 810 supplies readout pulses, one adapted to read out a reference signal and another adapted to read out a pixel signal output from each of the pixel circuits 850, to the signal readout circuit 880 via a reference signal readout control line 814 and pixel signal readout control line 815. Further, the timing control circuit 810 supplies a column scan control signal used to control the column scan circuit 830 via a column scan control line 817.
The row scan circuit 820 successively generates row scan signals based on a row address signal and timing signal supplied from the timing control circuit 810. The row scan signals are adapted to cause the pixel circuits 850 to output signals on a row-by-row basis. The row scan circuit 820 supplies the generated row scan signals to the horizontal lines (HL) 829.
Each of the pixel circuits 850 converts incident light or optical signal into an electric signal through photoelectric conversion. The pixel circuit 850 amplifies the electric signal with an FD amplifier that has a floating diffusion (FD).
On the other hand, each of the pixel circuits 850 includes a photoelectric conversion element 851, transfer transistor 852, reset transistor 853 and amplifying transistor 854. The photoelectric conversion element 851 generates electric charge commensurate with the light intensity.
The transfer transistor 852 transfers electrons, generated by the photoelectric conversion element 851, to the floating diffusion FD according to a transfer pulse supplied from the row scan circuit 820. The reset transistor 853 sets (charges) the floating diffusion FD to a constant reference potential according to a reset pulse supplied from the row scan circuit 820.
The amplifying transistor 854 amplifies the potential generated in the floating diffusion FD and outputs a signal commensurate with the amplified potential to the vertical signal line (VSL) 839. The amplifying transistor 854 forms a source follower circuit together with the load transistor 874. That is, the amplifying transistor 854 amplifies the potential generated in the floating diffusion FD according to the load current supplied from the load transistor 874.
The amplifying transistor 854 amplifies the reference potential generated in the floating diffusion FD and outputs the amplified reference potential to the vertical signal line (VSL) 839 as a reference potential. This reference signal is used by the CDS circuit 881 or 882 to remove specific noise components from the pixel circuits 850.
Further, the amplifying transistor 854 amplifies the potential generated as a result of the accumulation of the electrons, transferred from the transfer transistor 852, in the floating diffusion FD and outputs the amplified potential to the vertical signal line (VSL) 839 as a pixel signal.
The column scan circuit 830 generates an output control signal based on a row scan control signal supplied from the timing control circuit 810. The output control signal causes the signal readout circuit 880 to output the pixel signals of each column to the signal processing section 890. The column scan circuit 830 supplies the generated output control signal to the CDS circuits 881 and 882.
A reference current generation circuit 862 is a constant current circuit adapted to supply a reference current to a reference current line 863. The reference current generation circuit 862 supplies the generated reference current to the load current source circuit 860 via the reference current line 863.
The load current source circuit 860 supplies a load current to each of the vertical signal lines (VSL) 839 based on the reference current supplied from the reference current generation circuit 862. The reference transistor 861 causes the load transistor 874 in each column to generate a load current that is approximately equal to the reference current (bias current) supplied from the reference current generation circuit 862. The reference transistor 861 ensures that a constant load current is supplied to the vertical signal line in each column from the load transistor 874. That is, the reference transistor 861 forms a current mirror circuit together with the load transistor 874 in each column.
Each of the load transistors 874 supplies a load current, commensurate with the reference current supplied to the reference transistor 861, to the vertical signal line (VSL) 839. Further, each of the load transistors 874 supplies a load current, used to drive the amplifying transistors 854, to the vertical signal line (VSL) 839.
The parasitic capacitor 879 includes a parasitic capacitor generated between the gate and drain of the load transistor 874 and an interwire capacitor formed between the vertical signal line (VSL) 839 and a load transistor gate line 872. This parasitic capacitor 879 produces coupling between the vertical signal line (VSL) 839 and load transistor gate line 872 in each column. That is, the potential of the load transistor gate line 872 changes with change in the signal level of the vertical signal line (VSL) 839.
The signal readout circuit 880 subjects the pixel signals output from the pixel array section 840 to correlated double sampling, thus removing fixed pattern noise. The CDS circuits 881 and 882 read out the reference and pixel signals output from each of the pixel circuits 850 according to the readout pulses supplied via the reference signal readout control line 814 and pixel signal readout control line 815. The CDS circuits 881 and 882 take the difference in level between the reference and pixel signals to remove fixed pattern noise. The CDS circuits 881 and 882 supply the noise-free pixel signals to the signal processing section 890.
The signal processing section 890 converts each of the pixel signals, i.e., analog signals, supplied from the CDS circuits 881 and 882, into a digital signal. The signal processing section 890 outputs the digital signal to a signal output line 891 as an image signal.
As described above, the solid-state imaging device 800 removes noise components produced by the pixel circuits 850 through correlated double sampling.